1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to forming merged lines in a metallization layer.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by embedding copper lines and vias in a dielectric layer stack. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less. Copper lines and vias are typically formed by performing well-known damascene (single or dual) processes whereby trenches or openings are formed in a layer of insulating material. Thereafter, barrier layers are deposited in the trenches or openings followed by over-filling the trenches or openings with copper material. Next, a planarization process is performed to remove the excess materials above the insulating material, thereby leaving the resulting line or via positioned in the previously formed trench or opening.
In the case of copper lines, the width of the lines is typically limited by the photolithography processes used to pattern the trenches in the layer of insulating material. In the case where the lines are formed of a material that may be directly patterned, e.g., tungsten, the width of the patterned lines is still limited by photolithography processes. To improve the reliability of the patterning process, a large number of evenly spaced lines are typically formed in a regular pattern. The width of each line and the pitch between lines is determined by the patterning process. In an exemplary self-aligned technique, referred to as self-aligned double patterning (SADP), a hard mask layer is formed above a dielectric layer and a plurality of mandrel line elements is formed above the hard mask layer. Spacers are formed on sidewalls of the mandrel and the mandrel is removed, leaving the spacers as an etch mask for patterning the hard mask layer. The pitch of the spacers is effectively double that of the mandrel elements. Another technique, referred to as self-aligned quadruple patterning (SAQP) forms another set of spacers and removes the first set, effectively quadrupling the pitch of the mandrel elements. The patterned hard mask layer is used to etch trenches in the underlying dielectric layer, and the trenches are filled with metal to form the interconnect lines.
Due to the regular nature of the spacers and the self-aligned process, it is inherently difficult to pattern trenches with widths greater than the characteristic width of the patterning process, referred to as the 1× width. The patterning of wider lines, such as those needed for high current capacity power rails, typically requires additional masking and patterning steps, giving rise to increased fabrication complexity and cost.
The present disclosure is directed to various methods of forming merged lines in a metallization layer that may avoid, or at least reduce, the effects of one or more of the problems identified above.